Integrated photonics is currently a fast growing and increasingly mature technology that enables the production of low-cost, highly scalable integrated optical devices including circuits and components designed for applications in, for example, high speed optical communications, sensing and experimental physics. In particular, the design and development of integrated photonic devices provided on a Silicon On Insulator (SOI) wafer architecture is revolutionizing the field of optical communications, allowing the realization of compact, low power circuits that can be seamlessly integrated to electrical circuits, thus allowing for dense optical circuits integration.
Integrated optical components such as modulators, optical filters, photodetectors, arrayed waveguide gratings (AWGs), couplers, wavelength division multiplexers and all-optical wavelength converters have successfully been demonstrated, showing that multiple functions can be effectively integrated in a single integrated photonic chip. As these components can be now realized in μm-scale circuits, compact low power silicon photonic devices are now able to replace bulk components. For example, silicon photonic optical transceivers, packaged in standard QSFP28 form factor, are now available, supporting speeds up to 100 Gb/s, usable for high speed intra-data centre connections, which allows the replacement of copper cables and other bulk components.
Although the technology is already relatively mature, some significant technical challenges need to be addressed. For example, with ongoing developments in the technology, the number of photonic components within a product and the demands, and consequently complexity, of each device has been increasing. Thus, there is a constant need for smaller, higher density devices.
Current Photonic Integrated Circuit (PIC) chips are generally being designed to lay out photonic components and waveguides across the two-dimensional plane of the chip wafer such that the guiding and interaction of the light is constrained at a single ‘level’ or in a single photonic ‘layer’ within the device. In this two-dimensional, single layer PIC chip layout, the interconnecting optical waveguides can make up the bulk of the photonic devices. As a result, despite the promise of integrated photonics to miniaturise discrete optical components, PIC chips designs have not yet reached the circuit density of a microprocessor. For example, the current power transfer rate requirement for optical signals on a two-dimensional modulator chip of ˜100 fJ per bit has to meet the electronic driver circuit performance in terms of switching power, speed and thermal management.
Such a two-dimensional photonic circuit layout will be disadvantaged due to space restriction for integration with its electronic counterparts. This is restricting the uptake in the market of integrating multifunctional optical processing chips with integration with VLSI electronic chips. This limitation will have an impact on the development and large-scale adoption of PICs for optical data processing, in particular for communication and medical imaging applications. Despite this, the silicon photonics technology market value is already estimated to be USD 0.5 billion in 2017 and forecasted to grow to USD 1.6 billion by 2022. This evaluation is based on the existing two-dimensional discrete component systems such as transceivers, modulators and attenuators.
Therefore, solutions to increase the circuit density of PICs would facilitate the market adoption and further expansion of integrated photonics.
One approach to realising higher density optical systems would be to develop and fabricate PICs having a three-dimensional photonic integrated circuit architecture. In these three-dimensional PIC chip designs, integrated photonic circuits and components would be fabricated to be located at different “levels” or heights in the plane of the chip relative to each other. Such PIC chips may generally be referred to as “multilayer” PICs, as there may be integrated photonic components or circuits or ‘layered’ over another. A move to a three-dimensional PIC chip architecture would enable accommodation in the same chip wafer of more active and passive optical devices and, importantly, the optical interconnect waveguides that carry the signals within and between different layers within the same chip. This would allow for a denser integration that would further enhance the ability of PICs to provide commercially viable high circuit density functions of photonic detection, conditioning, modulation, multiplexing and demultiplexing (MUX-DEMUX). The introduction of higher density PICs using three-dimensional silicon photonics technology would thus add a new market share, especially in the data communication, healthcare imaging and sensor sectors. A move toward a three-dimensional or multilayer architecture that allows effective high-density PIC chips to be deployed is therefore desirable. Discrete photonic devices using a three-dimensional PIC architecture have been demonstrated in the lab, which perform a single operation, such as power splitting and coupling. However, there are no definitive three-dimension optical chips on the market.
It is in this context that the presently disclosure has been devised.